Отображение 1 - 8 результаты of 8 для поиска '"MOS transistor."', время запроса: 0.02сек. Отмена результатов
  1. 1

    A true-1-V 300-μW CMOS-subthreshold log-domain hearing-aid-on-chip. по Serra-Graells, F.

    Опубликовано в: IEEE Journal of solid state circuits
    Статья

    A true-1-V 300-μW CMOS-subthreshold log-domain hearing-aid-on-chip.
  2. 2

    Fully integrated voiceband codec in a standard digital CMOS technology. по Pernici, S.

    Опубликовано в: IEEE Journal of solid state circuits
    Статья

    Fully integrated voiceband codec in a standard digital CMOS technology.
  3. 3

    A CAD methodology for optimizing transistor current and sizing in analog CMOS design. по Binkley, D.M

    Статья

    A CAD methodology for optimizing transistor current and sizing in analog CMOS design.
  4. 4

    Hot-hole-induced dielectric breakdown in LDMOS transistors. по Labate, L.

    Опубликовано в: IEEE Transactions on electron devices
    Статья

    Hot-hole-induced dielectric breakdown in LDMOS transistors.
  5. 5

    A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors. по Inokawa, H.

    Опубликовано в: IEEE Transactions on electron devices
    Статья

    A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors.
  6. 6

    An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs. по Singh, R.

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs.
  7. 7

    A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors. по Inokawa, H.

    Опубликовано в: IEEE Transactions on electron devices
    Статья

    A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors.
  8. 8

    A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches. по Chua-Chin Wang

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches.

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