Отображение 1 - 4 результаты of 4 для поиска '"CMOS standard cell."', время запроса: 0.02сек. Отмена результатов
  1. 1

    Area-efficient high-throughput MAP decoder architectures. по Seok-Jun Lee

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    Area-efficient high-throughput MAP decoder architectures.
  2. 2

    Design and performance testing of a 2.29-GB по Verbauwhede, I.

    Опубликовано в: IEEE Journal of solid state circuits
    Статья

    Design and performance testing of a 2.29-GB
  3. 3

    A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. по Morioka, S.

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture.
  4. 4

    High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme. по Meng-Da Yang

    Опубликовано в: IEEE Transactions on VLSI systems
    Статья

    High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme.

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