ASIC design and synthesis RTL design using Verilog door Taraate, Vaibbhav

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Available for University of the Philippines System via SpringerLink. Click here to access

ASIC/SoC functional design verification a comprehensive guide to technologies and methodologies door Mehta, Ashok B.

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PLD based design with VHDL RTL design, synthesis and implementation door Taraate, Vaibbhav

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Model generation in electronic design

Logic design for array-based circuits a structured design methodology door White, Donnamaie E. 1942-

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Successful ASIC design the first time through door Huber, John P.

Non-RAM-based architectural designs of wavelet-based digital systems based on novel nonlinear I door Dongming Peng