検索結果 1 - 8 結果 / 8 検索語 '"MOS transistor."', 処理時間: 0.02秒 結果の絞り込み
  1. 1

    A true-1-V 300-μW CMOS-subthreshold log-domain hearing-aid-on-chip. 著者: Serra-Graells, F.

    論文

    A true-1-V 300-μW CMOS-subthreshold log-domain hearing-aid-on-chip.
  2. 2

    Fully integrated voiceband codec in a standard digital CMOS technology. 著者: Pernici, S.

    論文

    Fully integrated voiceband codec in a standard digital CMOS technology.
  3. 3

    A CAD methodology for optimizing transistor current and sizing in analog CMOS design. 著者: Binkley, D.M

    論文

    A CAD methodology for optimizing transistor current and sizing in analog CMOS design.
  4. 4

    Hot-hole-induced dielectric breakdown in LDMOS transistors. 著者: Labate, L.

    論文

    Hot-hole-induced dielectric breakdown in LDMOS transistors.
  5. 5

    A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors. 著者: Inokawa, H.

    論文

    A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors.
  6. 6

    An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs. 著者: Singh, R.

    論文

    An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs.
  7. 7

    A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors. 著者: Inokawa, H.

    論文

    A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors.
  8. 8

    A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches. 著者: Chua-Chin Wang

    論文

    A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches.

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