ASIC design and synthesis RTL design using Verilog 著者: Taraate, Vaibbhav

Also available remotely for the University of the Philippines System via SpringerLink. Click here to access thru EZproxy
Available for University of the Philippines System via SpringerLink. Click here to access

ASIC/SoC functional design verification a comprehensive guide to technologies and methodologies 著者: Mehta, Ashok B.

Available for University of the Philippines System via SpringerLink. Click here to access
Also available remotely for University of the Philippines System via SpringerLink. Click here to access thru EZproxy

PLD based design with VHDL RTL design, synthesis and implementation 著者: Taraate, Vaibbhav

Available for University of the Philippines Diliman via SpringerLink. Click here to access
Also available remotely for University of the Philippines Diliman via SpringerLink. Click here to access thru EZproxy

Model generation in electronic design

Logic design for array-based circuits a structured design methodology 著者: White, Donnamaie E. 1942-

Available for University of the Philippines System via ScienceDirect. Click here to access
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Successful ASIC design the first time through 著者: Huber, John P.

Non-RAM-based architectural designs of wavelet-based digital systems based on novel nonlinear I 著者: Dongming Peng