Showing 1 - 8 results of 8 for search '"MOS transistor."', सवाल का समय: 0.02सेकंड परिणाम को परिष्कृत करें
  1. 1

    A true-1-V 300-μW CMOS-subthreshold log-domain hearing-aid-on-chip. द्वारा Serra-Graells, F.

    में प्रकाशित IEEE Journal of solid state circuits
    लेख

    A true-1-V 300-μW CMOS-subthreshold log-domain hearing-aid-on-chip.
  2. 2

    Fully integrated voiceband codec in a standard digital CMOS technology. द्वारा Pernici, S.

    में प्रकाशित IEEE Journal of solid state circuits
    लेख

    Fully integrated voiceband codec in a standard digital CMOS technology.
  3. 3

    A CAD methodology for optimizing transistor current and sizing in analog CMOS design. द्वारा Binkley, D.M

    लेख

    A CAD methodology for optimizing transistor current and sizing in analog CMOS design.
  4. 4

    Hot-hole-induced dielectric breakdown in LDMOS transistors. द्वारा Labate, L.

    में प्रकाशित IEEE Transactions on electron devices
    लेख

    Hot-hole-induced dielectric breakdown in LDMOS transistors.
  5. 5

    A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors. द्वारा Inokawa, H.

    में प्रकाशित IEEE Transactions on electron devices
    लेख

    A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors.
  6. 6

    An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs. द्वारा Singh, R.

    में प्रकाशित IEEE Transactions on VLSI systems
    लेख

    An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs.
  7. 7

    A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors. द्वारा Inokawa, H.

    में प्रकाशित IEEE Transactions on electron devices
    लेख

    A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors.
  8. 8

    A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches. द्वारा Chua-Chin Wang

    में प्रकाशित IEEE Transactions on VLSI systems
    लेख

    A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches.

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