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1
VLSI physical design from graph partitioning to timing closure
Foilsithe / Cruthaithe 2011Available for the University of the Philippines Diliman via SpringerLink. Click here to access
Electronic Resource -
2
Timing analysis and simulation for signal integrity engineers
Foilsithe / Cruthaithe 2008Table of contents only
LEABHAR -
3
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4
Monolithic phase-locked loops and clock recovery circuits theory and design
Foilsithe / Cruthaithe 1996LEABHAR