Näytetään 1 - 4 yhteensä 4 tuloksesta haulle '"CMOS standard cell."', hakuaika: 0,02s Tarkenna hakua
  1. 1

    Area-efficient high-throughput MAP decoder architectures. Tekijä Seok-Jun Lee

    Artikkeli

    Area-efficient high-throughput MAP decoder architectures.
  2. 2

    Design and performance testing of a 2.29-GB Tekijä Verbauwhede, I.

    Artikkeli

    Design and performance testing of a 2.29-GB
  3. 3

    A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. Tekijä Morioka, S.

    Artikkeli

    A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture.
  4. 4

    High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme. Tekijä Meng-Da Yang

    Artikkeli

    High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme.

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