Erakusten 1 - 10 emaitzak -- 12 bilaketa honetara '"VLSI circuits."', Bilaketaren denbora: 0,02s Findu emaitzak
  1. 1

    The design of DNA self-assembled computing circuitry. nork Dwyer, C.

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    The design of DNA self-assembled computing circuitry.
  2. 2

    Toward the accurate prediction of placement wire length distributions in VLSI circuits. nork Dambre, J.

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    Toward the accurate prediction of placement wire length distributions in VLSI circuits.
  3. 3

    Analytical models and algorithms for the efficient signal integrity verification of inductance-effect-prominent multicoupled VLSI circuit interconnects. nork Seongkyun Shin

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    Analytical models and algorithms for the efficient signal integrity verification of inductance-effect-prominent multicoupled VLSI circuit interconnects.
  4. 4

    Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits. nork Maheshwari, A.

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits.
  5. 5

    Design of wireless on-wafer submicron characterization system. nork Moore, B.

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    Design of wireless on-wafer submicron characterization system.
  6. 6

    Efficient algorithms for multilevel power estimation of VLSI circuits. nork Bachmann, W.W

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    Efficient algorithms for multilevel power estimation of VLSI circuits.
  7. 7

    Cascaded Bayesian inferencing for switching activity estimation with correlated inputs. nork Bhanja, S.

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    Cascaded Bayesian inferencing for switching activity estimation with correlated inputs.
  8. 8

    Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. nork Pomeranz, I.

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations.
  9. 9

    Design of hierarchical cellular automata for on-chip test pattern generator. nork Sikdar, B.K

    Artikulua

    Design of hierarchical cellular automata for on-chip test pattern generator.
  10. 10

    Statistical analysis of subthreshold leakage current for VLSI circuits. nork Rao, R.

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    Statistical analysis of subthreshold leakage current for VLSI circuits.

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