Erakusten 1 - 3 emaitzak -- 3 bilaketa honetara '"Test cost reduction."', Bilaketaren denbora: 0,01s Findu emaitzak
  1. 1

    SOC test planning using virtual test access architectures. nork Sehgal, A.

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    SOC test planning using virtual test access architectures.
  2. 2

    Weighted pseudorandom hybrid BIST. nork Jas, A.

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    Weighted pseudorandom hybrid BIST.
  3. 3

    Low-power scan design using first-level supply gating. nork Bhunia, S.

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    Low-power scan design using first-level supply gating.

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