Erakusten 1 - 2 emaitzak -- 2 bilaketa honetara '"Static timing analysis."', Bilaketaren denbora: 0,02s Findu emaitzak
  1. 1

    Modeling subthreshold SOI logic for static timing analysis. nork Valentian, A.

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    Modeling subthreshold SOI logic for static timing analysis.
  2. 2

    Switch-factor based loop RLC modeling for efficient timing analysis. nork Yu Cao

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    Switch-factor based loop RLC modeling for efficient timing analysis.

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