Erakusten 1 - 4 emaitzak -- 4 bilaketa honetara '"CMOS standard cell."', Bilaketaren denbora: 0,02s Findu emaitzak
  1. 1

    Area-efficient high-throughput MAP decoder architectures. nork Seok-Jun Lee

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    Area-efficient high-throughput MAP decoder architectures.
  2. 2

    Design and performance testing of a 2.29-GB nork Verbauwhede, I.

    Artikulua

    Design and performance testing of a 2.29-GB
  3. 3

    A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. nork Morioka, S.

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture.
  4. 4

    High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme. nork Meng-Da Yang

    Argitaratua izan da IEEE Transactions on VLSI systems
    Artikulua

    High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme.

Bilaketa egiteko lanabesak: