Mostrando 1 - 4 Resultados de 4 Para Buscar '"CMOS standard cell."', tiempo de consulta: 0.02s Limitar resultados
  1. 1

    Area-efficient high-throughput MAP decoder architectures. por Seok-Jun Lee

    Artículo

    Area-efficient high-throughput MAP decoder architectures.
  2. 2

    Design and performance testing of a 2.29-GB por Verbauwhede, I.

    Artículo

    Design and performance testing of a 2.29-GB
  3. 3

    A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. por Morioka, S.

    Artículo

    A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture.
  4. 4

    High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme. por Meng-Da Yang

    Artículo

    High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme.

Herramientas de búsqueda: