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A true-1-V 300-μW CMOS-subthreshold log-domain hearing-aid-on-chip.
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Serra-Graells, F.
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IEEE Journal of solid state circuits
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Fully integrated voiceband codec in a standard digital CMOS technology.
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Pernici, S.
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A CAD methodology for optimizing transistor current and sizing in analog CMOS design.
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Binkley, D.M
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Hot-hole-induced dielectric breakdown in LDMOS transistors.
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Labate, L.
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A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors.
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Inokawa, H.
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An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs.
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Singh, R.
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A multiple-valued logic and memory with combined single-electron and metal-oxide-semiconductor transistors.
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Inokawa, H.
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A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches.
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Chua-Chin Wang
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DATABASE
Union Catalog (Buklod)
8 results
8
AUTHOR
Inokawa, H.
2 results
2
Binkley, D.M
1 results
1
Chua-Chin Wang
1 results
1
Labate, L.
1 results
1
Pernici, S.
1 results
1
Serra-Graells, F.
1 results
1
Singh, R.
1 results
1
see all…
RESOURCE TYPE
Article
8 results
8
LANGUAGE
English
8 results
8
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