Search Results - "Hardware implementation."

1

Architectures and protocols that enable new applications on opticalnetworks. by Veeraraghavan, M.

Published in IEEE Communications magazine

Article

Architectures and protocols that enable new applications on opticalnetworks.

2

High-speed VLSI architectures for the AES algorithm. by Xinmiao Zhang

Published in IEEE Transactions on VLSI systems

Article

High-speed VLSI architectures for the AES algorithm.

3

Design and implementation of low-energy turbo decoders. by Kaza, J.

Published in IEEE Transactions on VLSI systems

Article

Design and implementation of low-energy turbo decoders.

4

Systematic IEEE rounding method for high-speed floating-point multipliers. by Quach, N.T

Published in IEEE Transactions on VLSI systems

Article

Systematic IEEE rounding method for high-speed floating-point multipliers.

5

Memory energy minimization by data compression algorithms, architectures and implementation. by Benini, L.

Published in IEEE Transactions on VLSI systems

Article

Memory energy minimization by data compression algorithms, architectures and implementation.

6

Implementing scheduling algorithms in high-speed networks. by Stephens, D.C

Published in IEEE Journal on selected areas in communications

Article

Implementing scheduling algorithms in high-speed networks.

7

Characterization and modeling of in-building power lines for high-speed data transmission. by Tang, L.T

Published in IEEE Transactions on power delivery

Article

Characterization and modeling of in-building power lines for high-speed data transmission.

8

Fast factorization architecture in soft-decision Reed-Solomon decoding. by Xinmiao Zhang

Published in IEEE Transactions on VLSI systems

Article

Fast factorization architecture in soft-decision Reed-Solomon decoding.

9

A design methodology for networks of online modules and its application to the Levinson-Durbin algorithm. by Galli, R.

Published in IEEE Transactions on VLSI systems

Article

A design methodology for networks of online modules and its application to the Levinson-Durbin algorithm.

10

A digital vision chip specialized for high-speed target tracking. by Komuro, T.

Published in IEEE Transactions on electron devices

Article

Architectures and protocols that enable new applications on opticalnetworks. by Veeraraghavan, M.

High-speed VLSI architectures for the AES algorithm. by Xinmiao Zhang

Design and implementation of low-energy turbo decoders. by Kaza, J.

Systematic IEEE rounding method for high-speed floating-point multipliers. by Quach, N.T

Memory energy minimization by data compression algorithms, architectures and implementation. by Benini, L.

Implementing scheduling algorithms in high-speed networks. by Stephens, D.C

Characterization and modeling of in-building power lines for high-speed data transmission. by Tang, L.T

Fast factorization architecture in soft-decision Reed-Solomon decoding. by Xinmiao Zhang

A design methodology for networks of online modules and its application to the Levinson-Durbin algorithm. by Galli, R.

A digital vision chip specialized for high-speed target tracking. by Komuro, T.

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