Treffer 1 - 4 von 4 für Suche '"CMOS standard cell."', Suchdauer: 0,02s Treffer weiter einschränken
  1. 1

    Area-efficient high-throughput MAP decoder architectures. von Seok-Jun Lee

    Artikel

    Area-efficient high-throughput MAP decoder architectures.
  2. 2

    Design and performance testing of a 2.29-GB von Verbauwhede, I.

    Artikel

    Design and performance testing of a 2.29-GB
  3. 3

    A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. von Morioka, S.

    Artikel

    A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture.
  4. 4

    High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme. von Meng-Da Yang

    Artikel

    High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme.

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