Canlyniadau Chwilio - "Hardware implementation."

1

Architectures and protocols that enable new applications on opticalnetworks. gan Veeraraghavan, M.

Cyhoeddwyd yn IEEE Communications magazine

Erthygl

Architectures and protocols that enable new applications on opticalnetworks.

2

High-speed VLSI architectures for the AES algorithm. gan Xinmiao Zhang

Cyhoeddwyd yn IEEE Transactions on VLSI systems

Erthygl

High-speed VLSI architectures for the AES algorithm.

3

Design and implementation of low-energy turbo decoders. gan Kaza, J.

Cyhoeddwyd yn IEEE Transactions on VLSI systems

Erthygl

Design and implementation of low-energy turbo decoders.

4

Systematic IEEE rounding method for high-speed floating-point multipliers. gan Quach, N.T

Cyhoeddwyd yn IEEE Transactions on VLSI systems

Erthygl

Systematic IEEE rounding method for high-speed floating-point multipliers.

5

Memory energy minimization by data compression algorithms, architectures and implementation. gan Benini, L.

Cyhoeddwyd yn IEEE Transactions on VLSI systems

Erthygl

Memory energy minimization by data compression algorithms, architectures and implementation.

6

Implementing scheduling algorithms in high-speed networks. gan Stephens, D.C

Cyhoeddwyd yn IEEE Journal on selected areas in communications

Erthygl

Implementing scheduling algorithms in high-speed networks.

7

Characterization and modeling of in-building power lines for high-speed data transmission. gan Tang, L.T

Cyhoeddwyd yn IEEE Transactions on power delivery

Erthygl

Characterization and modeling of in-building power lines for high-speed data transmission.

8

Fast factorization architecture in soft-decision Reed-Solomon decoding. gan Xinmiao Zhang

Cyhoeddwyd yn IEEE Transactions on VLSI systems

Erthygl

Fast factorization architecture in soft-decision Reed-Solomon decoding.

9

A design methodology for networks of online modules and its application to the Levinson-Durbin algorithm. gan Galli, R.

Cyhoeddwyd yn IEEE Transactions on VLSI systems

Erthygl

A design methodology for networks of online modules and its application to the Levinson-Durbin algorithm.

10

A digital vision chip specialized for high-speed target tracking. gan Komuro, T.

Cyhoeddwyd yn IEEE Transactions on electron devices

Erthygl

Architectures and protocols that enable new applications on opticalnetworks. gan Veeraraghavan, M.

High-speed VLSI architectures for the AES algorithm. gan Xinmiao Zhang

Design and implementation of low-energy turbo decoders. gan Kaza, J.

Systematic IEEE rounding method for high-speed floating-point multipliers. gan Quach, N.T

Memory energy minimization by data compression algorithms, architectures and implementation. gan Benini, L.

Implementing scheduling algorithms in high-speed networks. gan Stephens, D.C

Characterization and modeling of in-building power lines for high-speed data transmission. gan Tang, L.T

Fast factorization architecture in soft-decision Reed-Solomon decoding. gan Xinmiao Zhang

A design methodology for networks of online modules and its application to the Levinson-Durbin algorithm. gan Galli, R.

A digital vision chip specialized for high-speed target tracking. gan Komuro, T.

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