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Digital logic design using Verilog coding and RTL synthesis
Publicat 2016Available for University of the Philippines System via SpringerLink. Click here to access
Also available remotely for University of the Philippines System via SpringerLink. Click here to access thru EZproxy
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Advanced digital logic design using VHDL, state machines, and synthesis for FPGAs
Publicat 2006Llibre -
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Advanced digital logic design using Verilog, state machines, and synthesis for FPGAs
Publicat 2006Llibre