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  1. 1

    An integration-biased BER-aware design methodology of a BPSK transceiver front-end for power line sensor nodes od Ortiz, Joana Rochelle R.

    Izdano 2014
    Thesis

    An integration-biased BER-aware design methodology of a BPSK transceiver front-end for power line sensor nodes
  2. 2

    PVT-aware digital techniques for low-power, 0.5V, on-chip processing unit for the SmartWire node in 65nm CMOS process od Sebastian, Sherry Joy Alvionne

    Izdano 2014
    Thesis

    PVT-aware digital techniques for low-power, 0.5V, on-chip processing unit for the SmartWire node in 65nm CMOS process

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