Mostrando 1 - 2 resultados de 2 para a busca '', tempo de busca: 0.01s Refinar Resultados
  1. 1

    An integration-biased BER-aware design methodology of a BPSK transceiver front-end for power line sensor nodes por Ortiz, Joana Rochelle R.

    Publicado em 2014
    Tese

    An integration-biased BER-aware design methodology of a BPSK transceiver front-end for power line sensor nodes
  2. 2

    PVT-aware digital techniques for low-power, 0.5V, on-chip processing unit for the SmartWire node in 65nm CMOS process por Sebastian, Sherry Joy Alvionne

    Publicado em 2014
    Tese

    PVT-aware digital techniques for low-power, 0.5V, on-chip processing unit for the SmartWire node in 65nm CMOS process

Ferramentas de busca: