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  1. 1

    Implementation of local voltage dithering on the ARM7 microprocessor in a 90nm CMOS process 著者: Cada, Mark Angelo A.

    出版事項 2011
    学位論文

    Implementation of local voltage dithering on the ARM7 microprocessor in a 90nm CMOS process
  2. 2

    A USB 2.0 controller for an ARM7TDM-S processor implemented in FPGA 著者: Difuntorum, John Keithley L.

    出版事項 2011
    学位論文

    A USB 2.0 controller for an ARM7TDM-S processor implemented in FPGA
  3. 3

    SCARM a memory simulator with a compiler-assembler for the 32-bit ARM7 microprocessor 著者: Barahan, Nicole John Antonio

    出版事項 2011
    学位論文

    SCARM a memory simulator with a compiler-assembler for the 32-bit ARM7 microprocessor
  4. 4

    Design and implementation of a 32-Bit dual core capable DLX microprocessor with single-level cache 著者: Dioquino, Darryl Aldrin M.

    出版事項 2007
    学位論文

    Design and implementation of a 32-Bit dual core capable DLX microprocessor with single-level cache
  5. 5

    C compiler back end for the 32-bit dual core capable DLX microprocessor 著者: Ostrea, Allan Michael M.

    出版事項 2007
    学位論文

    C compiler back end for the 32-bit dual core capable DLX microprocessor
  6. 6

    A study of floating-point architectures for pipelined RISC processors 著者: Reyes, Joy Alinda P.

    出版事項 2005
    学位論文

    A study of floating-point architectures for pipelined RISC processors
  7. 7

    A study of selective power-down techniques for low-power RISC microprocessor design 著者: Khalid, Sihawi Abdulhamid

    出版事項 2004
    学位論文

    A study of selective power-down techniques for low-power RISC microprocessor design
  8. 8

    A study of selective power-down optimization techniques for low-power integrated RISC execution unit design 著者: Bantug, Arianne Contemprato

    出版事項 2003
    学位論文

    A study of selective power-down optimization techniques for low-power integrated RISC execution unit design
  9. 9

    A study of data transfer mechanisms in a RISC microprocessor augmented with a tightly coupled reconfigurable processing element (RPE) 著者: Alarcon, Louis Poblete

    出版事項 2002
    学位論文

    A study of data transfer mechanisms in a RISC microprocessor augmented with a tightly coupled reconfigurable processing element (RPE)
  10. 10

    32-bit pipelined RISC microprocessor 著者: Lee, Leonard

    論文

    32-bit pipelined RISC microprocessor

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