Đang hiển thị 1 - 9 kết quả của 9 cho tìm kiếm '', thời gian truy vấn: 0.01s Tinh chỉnh kết quả
  1. 1

    Less-reused filtering and live time prediction in multi-core processors with a shared L2 cache Bằng Dioquino, Darryl Aldrin M.

    Được phát hành 2013
    Luận văn

    Less-reused filtering and live time prediction in multi-core processors with a shared L2 cache
  2. 2

    A study of snoopy cache coherence protocols for dual processor systems Bằng Fernandez, Edward Bryann C.

    Được phát hành 2007
    Luận văn

    A study of snoopy cache coherence protocols for dual processor systems
  3. 3

    A study of translation look aside buffer structures for low power consumption Bằng Ballesil, Anastacia P.

    Xuất bản năm Philippine Engineering Journal (2007)
    Bài viết

    A study of translation look aside buffer structures for low power consumption
  4. 4

    The Cache-coherence problem in shared-memory multiprocessors hardware solutions

    Được phát hành 1993
    Sách

    The Cache-coherence problem in shared-memory multiprocessors hardware solutions
  5. 5

    Cache and interconnect architectures in multiprocessors

    Được phát hành 1990
    Sách

    Cache and interconnect architectures in multiprocessors
  6. 6

    Address scalability bottlenecks with distributed caching. Bằng Khan, Iqbal

    Xuất bản năm MSDN magazine
    Bài viết

    Address scalability bottlenecks with distributed caching.
  7. 7

    A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design Bằng Zarsuela, Jestoni V.

    Luận văn

    A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design
  8. 8

    RT-CaCC towards a cache-aware congestion control mechanism in wireless sensor networks Bằng Alipio, Melchizedek I.

    Luận văn

    RT-CaCC towards a cache-aware congestion control mechanism in wireless sensor networks
  9. 9

    Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache Bằng Alidio, Lianne

    Luận văn

    Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache

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