Gösterilen 1 - 9 sonuçlar arası kayıtlar. 9 sonuç. Aranan kelime '', Sorgu süresi: 0.01s Sonuçları Daraltın
  1. 1

    Less-reused filtering and live time prediction in multi-core processors with a shared L2 cache Yazar: Dioquino, Darryl Aldrin M.

    Baskı/Yayın Bilgisi 2013
    Tez

    Less-reused filtering and live time prediction in multi-core processors with a shared L2 cache
  2. 2

    A study of snoopy cache coherence protocols for dual processor systems Yazar: Fernandez, Edward Bryann C.

    Baskı/Yayın Bilgisi 2007
    Tez

    A study of snoopy cache coherence protocols for dual processor systems
  3. 3

    A study of translation look aside buffer structures for low power consumption Yazar: Ballesil, Anastacia P.

    Yayımlandı Philippine Engineering Journal (2007)
    Makale

    A study of translation look aside buffer structures for low power consumption
  4. 4

    The Cache-coherence problem in shared-memory multiprocessors hardware solutions

    Baskı/Yayın Bilgisi 1993
    Kitap

    The Cache-coherence problem in shared-memory multiprocessors hardware solutions
  5. 5

    Cache and interconnect architectures in multiprocessors

    Baskı/Yayın Bilgisi 1990
    Kitap

    Cache and interconnect architectures in multiprocessors
  6. 6

    Address scalability bottlenecks with distributed caching. Yazar: Khan, Iqbal

    Yayımlandı MSDN magazine
    Makale

    Address scalability bottlenecks with distributed caching.
  7. 7

    A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design Yazar: Zarsuela, Jestoni V.

    Tez

    A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design
  8. 8

    RT-CaCC towards a cache-aware congestion control mechanism in wireless sensor networks Yazar: Alipio, Melchizedek I.

    Tez

    RT-CaCC towards a cache-aware congestion control mechanism in wireless sensor networks
  9. 9

    Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache Yazar: Alidio, Lianne

    Tez

    Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache

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