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Less-reused filtering and live time prediction in multi-core processors with a shared L2 cache
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Dioquino, Darryl Aldrin M.
Izdano 2013
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A study of snoopy cache coherence protocols for dual processor systems
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Fernandez, Edward Bryann C.
Izdano 2007
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A study of translation look aside buffer structures for low power consumption
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Ballesil, Anastacia P.
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Philippine Engineering Journal
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The Cache-coherence problem in shared-memory multiprocessors hardware solutions
Izdano 1993
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Cache and interconnect architectures in multiprocessors
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A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design
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Zarsuela, Jestoni V.
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RT-CaCC towards a cache-aware congestion control mechanism in wireless sensor networks
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Alipio, Melchizedek I.
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Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache
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Alidio, Lianne
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