1 - 8 toradh á dtaispeáint as 8 toradh san iomlán ar an gcuardach '', am iarratais: 0.01s Beachtaigh na torthaí
  1. 1

    Less-reused filtering and live time prediction in multi-core processors with a shared L2 cache de réir Dioquino, Darryl Aldrin M.

    Foilsithe / Cruthaithe 2013
    Tráchtas

    Less-reused filtering and live time prediction in multi-core processors with a shared L2 cache
  2. 2

    A study of snoopy cache coherence protocols for dual processor systems de réir Fernandez, Edward Bryann C.

    Foilsithe / Cruthaithe 2007
    Tráchtas

    A study of snoopy cache coherence protocols for dual processor systems
  3. 3

    A study of translation look aside buffer structures for low power consumption de réir Ballesil, Anastacia P.

    Foilsithe in Philippine Engineering Journal (2007)
    Alt

    A study of translation look aside buffer structures for low power consumption
  4. 4

    The Cache-coherence problem in shared-memory multiprocessors hardware solutions

    Foilsithe / Cruthaithe 1993
    LEABHAR

    The Cache-coherence problem in shared-memory multiprocessors hardware solutions
  5. 5

    Cache and interconnect architectures in multiprocessors

    Foilsithe / Cruthaithe 1990
    LEABHAR

    Cache and interconnect architectures in multiprocessors
  6. 6

    A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design de réir Zarsuela, Jestoni V.

    Tráchtas

    A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design
  7. 7

    RT-CaCC towards a cache-aware congestion control mechanism in wireless sensor networks de réir Alipio, Melchizedek I.

    Tráchtas

    RT-CaCC towards a cache-aware congestion control mechanism in wireless sensor networks
  8. 8

    Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache de réir Alidio, Lianne

    Tráchtas

    Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache

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