Näytetään 1 - 9 yhteensä 9 tuloksesta haulle '', hakuaika: 0,01s Tarkenna hakua
  1. 1

    Less-reused filtering and live time prediction in multi-core processors with a shared L2 cache Tekijä Dioquino, Darryl Aldrin M.

    Julkaistu 2013
    Opinnäyte

    Less-reused filtering and live time prediction in multi-core processors with a shared L2 cache
  2. 2

    A study of snoopy cache coherence protocols for dual processor systems Tekijä Fernandez, Edward Bryann C.

    Julkaistu 2007
    Opinnäyte

    A study of snoopy cache coherence protocols for dual processor systems
  3. 3

    A study of translation look aside buffer structures for low power consumption Tekijä Ballesil, Anastacia P.

    Julkaisussa Philippine Engineering Journal (2007)
    Artikkeli

    A study of translation look aside buffer structures for low power consumption
  4. 4

    The Cache-coherence problem in shared-memory multiprocessors hardware solutions

    Julkaistu 1993
    Kirja

    The Cache-coherence problem in shared-memory multiprocessors hardware solutions
  5. 5

    Cache and interconnect architectures in multiprocessors

    Julkaistu 1990
    Kirja

    Cache and interconnect architectures in multiprocessors
  6. 6

    Address scalability bottlenecks with distributed caching. Tekijä Khan, Iqbal

    Julkaisussa MSDN magazine
    Artikkeli

    Address scalability bottlenecks with distributed caching.
  7. 7

    A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design Tekijä Zarsuela, Jestoni V.

    Opinnäyte

    A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design
  8. 8

    RT-CaCC towards a cache-aware congestion control mechanism in wireless sensor networks Tekijä Alipio, Melchizedek I.

    Opinnäyte

    RT-CaCC towards a cache-aware congestion control mechanism in wireless sensor networks
  9. 9

    Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache Tekijä Alidio, Lianne

    Opinnäyte

    Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache

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