Treffer 1 - 8 von 8 für Suche '', Suchdauer: 0,02s Treffer weiter einschränken
  1. 1

    Less-reused filtering and live time prediction in multi-core processors with a shared L2 cache von Dioquino, Darryl Aldrin M.

    Veröffentlicht 2013
    Abschlussarbeit

    Less-reused filtering and live time prediction in multi-core processors with a shared L2 cache
  2. 2

    A study of snoopy cache coherence protocols for dual processor systems von Fernandez, Edward Bryann C.

    Veröffentlicht 2007
    Abschlussarbeit

    A study of snoopy cache coherence protocols for dual processor systems
  3. 3

    A study of translation look aside buffer structures for low power consumption von Ballesil, Anastacia P.

    Veröffentlicht in Philippine Engineering Journal (2007)
    Artikel

    A study of translation look aside buffer structures for low power consumption
  4. 4

    The Cache-coherence problem in shared-memory multiprocessors hardware solutions

    Veröffentlicht 1993
    Buch

    The Cache-coherence problem in shared-memory multiprocessors hardware solutions
  5. 5

    Cache and interconnect architectures in multiprocessors

    Veröffentlicht 1990
    Buch

    Cache and interconnect architectures in multiprocessors
  6. 6

    A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design von Zarsuela, Jestoni V.

    Abschlussarbeit

    A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design
  7. 7

    RT-CaCC towards a cache-aware congestion control mechanism in wireless sensor networks von Alipio, Melchizedek I.

    Abschlussarbeit

    RT-CaCC towards a cache-aware congestion control mechanism in wireless sensor networks
  8. 8

    Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache von Alidio, Lianne

    Abschlussarbeit

    Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache

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