Dangos 1 - 8 canlyniadau o 8 ar gyfer chwilio '', amser ymholiad: 0.02e Mireinio'r Canlyniadau
  1. 1

    Less-reused filtering and live time prediction in multi-core processors with a shared L2 cache gan Dioquino, Darryl Aldrin M.

    Cyhoeddwyd 2013
    Traethawd Ymchwil

    Less-reused filtering and live time prediction in multi-core processors with a shared L2 cache
  2. 2

    A study of snoopy cache coherence protocols for dual processor systems gan Fernandez, Edward Bryann C.

    Cyhoeddwyd 2007
    Traethawd Ymchwil

    A study of snoopy cache coherence protocols for dual processor systems
  3. 3

    A study of translation look aside buffer structures for low power consumption gan Ballesil, Anastacia P.

    Cyhoeddwyd yn Philippine Engineering Journal (2007)
    Erthygl

    A study of translation look aside buffer structures for low power consumption
  4. 4

    The Cache-coherence problem in shared-memory multiprocessors hardware solutions

    Cyhoeddwyd 1993
    Llyfr

    The Cache-coherence problem in shared-memory multiprocessors hardware solutions
  5. 5

    Cache and interconnect architectures in multiprocessors

    Cyhoeddwyd 1990
    Llyfr

    Cache and interconnect architectures in multiprocessors
  6. 6

    A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design gan Zarsuela, Jestoni V.

    Traethawd Ymchwil

    A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design
  7. 7

    RT-CaCC towards a cache-aware congestion control mechanism in wireless sensor networks gan Alipio, Melchizedek I.

    Traethawd Ymchwil

    RT-CaCC towards a cache-aware congestion control mechanism in wireless sensor networks
  8. 8

    Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache gan Alidio, Lianne

    Traethawd Ymchwil

    Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache

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