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  1. 1

    Less-reused filtering and live time prediction in multi-core processors with a shared L2 cache per Dioquino, Darryl Aldrin M.

    Publicat 2013
    Thesis

    Less-reused filtering and live time prediction in multi-core processors with a shared L2 cache
  2. 2

    A study of snoopy cache coherence protocols for dual processor systems per Fernandez, Edward Bryann C.

    Publicat 2007
    Thesis

    A study of snoopy cache coherence protocols for dual processor systems
  3. 3

    A study of translation look aside buffer structures for low power consumption per Ballesil, Anastacia P.

    Publicat a Philippine Engineering Journal (2007)
    Article

    A study of translation look aside buffer structures for low power consumption
  4. 4

    The Cache-coherence problem in shared-memory multiprocessors hardware solutions

    Publicat 1993
    Llibre

    The Cache-coherence problem in shared-memory multiprocessors hardware solutions
  5. 5

    Cache and interconnect architectures in multiprocessors

    Publicat 1990
    Llibre

    Cache and interconnect architectures in multiprocessors
  6. 6

    A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design per Zarsuela, Jestoni V.

    Thesis

    A study of cache sub-ranking and block buffering as power reduction techniques for multiprocessor cache design
  7. 7

    RT-CaCC towards a cache-aware congestion control mechanism in wireless sensor networks per Alipio, Melchizedek I.

    Thesis

    RT-CaCC towards a cache-aware congestion control mechanism in wireless sensor networks
  8. 8

    Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache per Alidio, Lianne

    Thesis

    Implementation of a 32-bit dual core ARM7 microprocessor with split-private level one cache and shared level two data cache

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