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  1. 1

    Power reduction techniques and BIST implementation on a DLX microprocessor using a 90nm CMOS process por Agbayani, Jay-ar Anacleto

    Publicado em 2010
    Tese

    Power reduction techniques and BIST implementation on a DLX microprocessor using a 90nm CMOS process
  2. 2

    Tutorial test generation for VLSI chips

    Publicado em 1988
    Livro

    Tutorial test generation for VLSI chips
  3. 3

    Automatic testing and evaluation of digital integrated circuits por Healy, James Thomas 1940-

    Publicado em 1981
    Livro

    Automatic testing and evaluation of digital integrated circuits
  4. 4

    Power optimized partial scan BIST implementation on DLX microprocessor por Buenaventura, Arvi D.

    Tese

    Power optimized partial scan BIST implementation on DLX microprocessor

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