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1
ASIC design and synthesis RTL design using Verilog
Foilsithe / Cruthaithe 2021Also available remotely for the University of the Philippines System via SpringerLink. Click here to access thru EZproxy
Available for University of the Philippines System via SpringerLink. Click here to access
Electronic Resource -
2
Digitally enhanced mixed signal systems
Foilsithe / Cruthaithe 2019Available for University of the Philippines Diliman via IET Digital Library. Click here to access
Also available remotely for University of the Philippines Diliman via IET Digital Library. Click here to access thru EZproxy
Electronic Resource -
3
ASIC/SoC functional design verification a comprehensive guide to technologies and methodologies
Foilsithe / Cruthaithe 2018Available for University of the Philippines System via SpringerLink. Click here to access
Also available remotely for University of the Philippines System via SpringerLink. Click here to access thru EZproxy
Electronic Resource -
4
PLD based design with VHDL RTL design, synthesis and implementation
Foilsithe / Cruthaithe 2017Available for University of the Philippines Diliman via SpringerLink. Click here to access
Also available remotely for University of the Philippines Diliman via SpringerLink. Click here to access thru EZproxy
Electronic Resource -
5
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6
VLSI design a practical guide for FPGA and ASIC implementations
Foilsithe / Cruthaithe 2011Available for the University of the Philippines Diliman via SpringerLink. Click here to access
Electronic Resource -
7
Hardware implementation of finite-field arithmetic
Foilsithe / Cruthaithe 2009Available for University of the Philippines Diliman via McGraw-Hill Access Engineering. Click here to access
Also available remotely for University of the Philippines Diliman via McGraw-Hill Access Engineering. Click here to access thru EZproxy
Electronic Resource -
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9
Closing the power gap between ASIC & custom tools and techniques for low power design
Foilsithe / Cruthaithe 2007Table of contents only
LEABHAR -
10
Advanced digital logic design using VHDL, state machines, and synthesis for FPGAs
Foilsithe / Cruthaithe 2006LEABHAR