TY  - GEN
T1  - Logic synthesis and SOC prototyping RTL design using VHDL
A1  - Taraate, Vaibbhav
LA  - English
PP  - Singapore
PB  - Springer
YR  - 2020
UL  - https://tuklas.up.edu.ph/Record/UP-99796217613997600
SN  - 9789811513145 (online ISBN)
KW  - Electronic circuits.
KW  - Microprogramming.
KW  - Logic design.
KW  - Circuits and Systems.
KW  - Control Structures and Microprogramming.
KW  - Logic Design.
KW  - Electronic books.
ER  -