APA (7th ed.) Citation

Taraate, V. (2020). Logic synthesis and SOC prototyping: RTL design using VHDL. Springer. https://doi.org/10.1007/978-981-15-1314-5

Chicago Style (17th ed.) Citation

Taraate, Vaibbhav. Logic Synthesis and SOC Prototyping: RTL Design Using VHDL. Singapore: Springer, 2020. https://doi.org/10.1007/978-981-15-1314-5.

MLA (9th ed.) Citation

Taraate, Vaibbhav. Logic Synthesis and SOC Prototyping: RTL Design Using VHDL. Springer, 2020. https://doi.org/10.1007/978-981-15-1314-5.