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Taraate, V. (2020). Logic synthesis and SOC prototyping: RTL design using VHDL. Springer. https://doi.org/10.1007/978-981-15-1314-5

Citación estilo Chicago

Taraate, Vaibbhav. Logic Synthesis and SOC Prototyping: RTL Design Using VHDL. Singapore: Springer, 2020. https://doi.org/10.1007/978-981-15-1314-5.

Cita MLA

Taraate, Vaibbhav. Logic Synthesis and SOC Prototyping: RTL Design Using VHDL. Springer, 2020. https://doi.org/10.1007/978-981-15-1314-5.