TY  - GEN
T1  - Advanced HDL synthesis and SOC prototyping RTL design using verilog
A1  - Taraate, Vaibbhav
LA  - English
PP  - Singapore
PB  - Springer
YR  - 2019
ED  - First edition.
UL  - https://tuklas.up.edu.ph/Record/UP-99796217613727830
SN  - 9789811087769 (eBook ISBN)
KW  - Electronic circuits.
KW  - Logic design.
KW  - Microprogramming.
KW  - Electronic books.
ER  -