Cita APA (7a ed.)

Jayanthy, S., & Bhuvaneswari, M. (2019). Test generation of crosstalk delay faults in VLSI circuits (First edition.). Springer. https://doi.org/10.1007/978-981-13-2493-2

Cita Chicago Style (17a ed.)

Jayanthy, S., y M.C Bhuvaneswari. Test Generation of Crosstalk Delay Faults in VLSI Circuits. First edition. Singapore: Springer, 2019. https://doi.org/10.1007/978-981-13-2493-2.

Cita MLA (9a ed.)

Jayanthy, S., y M.C Bhuvaneswari. Test Generation of Crosstalk Delay Faults in VLSI Circuits. First edition. Springer, 2019. https://doi.org/10.1007/978-981-13-2493-2.