Design techniques for mash continuous-time delta-sigma modulators Qiyuan Liu, Alexander Edward, Carlos Briseno-Vidrios, Jose Silva-Martinez. - Liu, Qiyuan; Edward, Alexander; Briseno-Vidrios, Carlos; Silva-Martinez, Jose; SpringerLink (Online service). (Cham Springer International Publishing, 2018)
Introduction -- Analog-To-Digital and Digital-To-Analog Converters -- Delta-Sigma Modulators -- Design Considerations Of Mash CT-ΔΣM -- A 43 mW MASH 2-2 CT ΔΣ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40nm CMOS -- A 50-MHz BW 67.3-dB SNDR MASH 1-1-1 CT ΔΣ Modulator with FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS -- A 4-Bit Continuous-Time ΔΣ Modulator with Fully Digital Quantizer Noise Reduction Algorithm Employing a 7-bit Quantizer -- Conclusion.
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Keywords: Systems engineering; Computer science; Electronic books