Lourenco, N., Martins, R., & Horta, N. C. G. (2017). Automatic analog IC sizing and optimization constrained with PVT corners and layout effects. Springer. https://doi.org/10.1007/978-3-319-42037-0
शिकागो शैली (17वां संस्करण) प्रशस्ति पत्रLourenco, Nuno, Ricardo Martins, और Nuno C. G. Horta. Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects. Cham: Springer, 2017. https://doi.org/10.1007/978-3-319-42037-0.
एमएलए (9वां संस्करण) प्रशस्ति पत्रLourenco, Nuno, et al. Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects. Springer, 2017. https://doi.org/10.1007/978-3-319-42037-0.
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