A logic function reduction and minimization algorithm for microcomputers - Ramirez, Rafael S. (Philippine Engineering Journal)
Combinational logic forms the basis of any digital system when decomposed into its basic elements. Of particular significance in this area is the reduction and minimization of a combinational logic function. Besides being a necessary educational stepping stone towards more complex sequential logic systems, it still bears its importance today in fault analysis of digital systems, applications involving Field Programmable Logic Arrays (FPLAs), or chip-level design requirements for LSI and VLSI technology. This paper proposes and describes a departure from the more popular Quine-McCluskey computer solution in the form of an algorithm based on variable partitioning, combination generation and searching techniques for the prime implicants. Minimization is done by using a Zero-One Integer Programming model of the problem where the implicants and the logic function minterms or maxterms form a set of constraints to the problem and an objective function is used based on a pseudo-cost efficient for each implicant requirement on fan-in and number of inverters. The algorithm