00000cmm a22000004i 4500 UP-99796217612749719 Buklod 20230215105418.0 m |o d | ta 141014s2015 xx o u | eng d 9783319019970 (online ISBN) (iLib)UPD-00362013758 WaSeSS DENGII rda eng DMLUC TK 7871.99 M44 A45 2015eb Alioto, Massimo author. Flip-flop design in nanometer CMOS from high speed to low energy Massimo Alioto, Elio Consoli, Gaetano Palumbo. Cham Springer International Publishing [2015] 1 online resource. text rdacontent computer rdamedia online resource rdacarrier The Logical Effort Method -- Design in the Energy-Delay Space -- Clocked Storage Elements -- Flip-Flop Optimized Design -- Analysis and Comparison in the Energy-Delay-Area Domain -- Energy Efficiency Versus Clock Slope -- Hold Time Issues and Impact of variations on Flip-Flop Topologies -- Ultra-Fast and Energy-Efficient Pulsed Latch Topologies. IP-based subscription, on-campus and remote access. Access via Electronic Resources of the UPD Engineering Library and University Library websites. This book provides a unified treatment of Flip-Flop design and selection in nanometer CMOS VLSI systems. The design aspects related to the energy-delay tradeoff in Flip-Flops are discussed, including their energy-optimal selection according to the targeted application, and the detailed circuit design in nanometer CMOS VLSI systems. Design strategies are derived in a coherent framework that includes explicitly nanometer effects, including leakage, layout parasitics, and process/voltage/temperature variations, as main advances over the existing body of work in the field. The related design tradeoffs are explored in a wide range of applications and the related energy-performance targets. A wide range of existing and recently proposed Flip-Flop topologies are discussed. Theoretical foundations are provided to set the stage for the derivation of design guidelines, and the emphasis is given on practical aspects and consequences of the presented results. Analytical models and derivations are introduced when needed to gain an insight into the inter-dependence of design parameters under practical constraints. This book serves as a valuable reference for practicing engineers working in the VLSI design area, and as a text book for senior undergraduate, graduate and postgraduate students (already familiar with digital circuits and timing). ? Provides a unified treatment of Flip-Flop design and energy/variation-aware selection in nanometer CMOS VLSI systems? Offers an in-depth analysis of the impact of nanometer effects on design tradeoffs? Presents a comprehensive analysis, by considering more than 20 topologies covering all relevant classes of circuits? Uses a rigorous framework based on novel methodologies to include layout parasitics within the circuit design loop. Electronic reproduction. New York SpringerLink 2015. Available via World Wide Web through SpringerLink. Metal oxide semiconductors, Complementary Design and construction. Flip chip technology. Integrated circuits Very large scale integration Design and construction. Electronic books. Consoli, Elio author. Palumbo, Gaetano author. SpringerLink (Online service). Electronic Resource https://dx.doi.org/10.1007/978-3-319-01997-0 Available for University of the Philippines System via SpringerLink. Click here to access https://link-springer-com.ezproxy.engglib.upd.edu.ph/book/10.1007%2F978-3-319-01997-0 Also available remotely for University of the Philippines System via SpringerLink. Click here to access thru EZproxy (viewed 15 June 2019) FO UPD DENG-II Electronic Resource