PVT-aware digital techniques for low-power, 0.5V, on-chip processing unit for the SmartWire node in 65nm CMOS process - Sebastian, Sherry Joy Alvionne (Quezon City College of Engineering, University of the Philippines Diliman, 2014)
Challenges in designing the SmartWire node include voltage variation of 475mV to 500mV and temperature variation of 0° to 120°C on top of process variations while maintaining a maximum chip area of 5mm^2. However, because current digital design methodologies do not consider these challenges, failures during the integration of the processing unit to the energy peripheral and data peripheral subsystems were encountered. These failures include: 1) timing failure due to the operation of digital blocks below a critical voltage of 475mV, and 2) communication failure due to the increase in bit error rate of the receive operation. In this thesis, these problems were addressed using 4 digital algorithmic techniques: wait state, time slot, frequency synchronization, and phase correction. Using theses techniques, timing failures were avoided by maintaining the voltage level above 475mV and communication failures during receive were addressed resulting in a bit error rate of 10^-4. Because of these techniques, the Smartwire node was successfully fabricated in 65nm CMOS process with an area of 4.84mm^2
Thesis (M.S. Electrical Engineering)--University of the Philippines, Diliman.
Keywords: Wireless sensor nodes -- Design and construction; Wireless sensor networks -- Fault tolerance; SmartWire