APA (7th ed.) Citation

Sebastian, S. J. A. (2014). PVT-aware digital techniques for low-power, 0.5V, on-chip processing unit for the SmartWire node in 65nm CMOS process. College of Engineering, University of the Philippines Diliman.

Chicago Style (17th ed.) Citation

Sebastian, Sherry Joy Alvionne. PVT-aware Digital Techniques for Low-power, 0.5V, On-chip Processing Unit for the SmartWire Node in 65nm CMOS Process. Quezon City: College of Engineering, University of the Philippines Diliman, 2014.

MLA (9th ed.) Citation

Sebastian, Sherry Joy Alvionne. PVT-aware Digital Techniques for Low-power, 0.5V, On-chip Processing Unit for the SmartWire Node in 65nm CMOS Process. College of Engineering, University of the Philippines Diliman, 2014.