A design methodology for implementing RF CMOS low noise amplifiers in a 0.25 uM CMOS process

A design methodology for implementing RF CMOS low noise amplifiers in a 0.25 uM CMOS process

In this paper, a methodology in designing CMOS Low Noise Amplifiers (LNAs) in a 0.25 um CMOS process is proposed. Three power matching techniques are considered in the design of the LNA. These are: (1) matching for maximum available gain, (2) matching for a constant gain, and (3) matching for stabil...

Disgrifiad llawn

Manylion Llyfryddiaeth
Cyhoeddwyd yn:Philippine Engineering Journal 29, 2(3 copies) (2008(D)).
Prif Awdur: Gusad-De Leon, Maria Theresa
Awduron Eraill: Alarcon, Louis P.
Fformat: Erthygl
Iaith:English
Pynciau:
Metal oxide semiconductors, Complementary > Testing.
Low noise amplifiers.
Mynediad Ar-lein:Also available online for University of the Philippines Diliman. Click here