BER-aware, PVT-resilient, all-digital BPSK demodulator for energy harvesting sensor nodes - Chua, Adelson Ng (College of Engineering, University of the Philippines Diliman, 2014)
The typical approach in achieveing a target bit error rate (BER) is to over-design the analog front-end receivers to compensate for the signal distortions due to process-voltage-temperature (PVT) variations. However, for energy-constrained systems, an all-digital demodulation and signal processing system is an attractive option since it enables error correction while relaxing the specifications for high-power analog blocks. In this thesis, 450 kHz BPSK correlation and carrier recovery algorithms were designed and implemented in a digital 65nm CMOS process. By exploiting zero-mean phase distortion of received signals, the target BER of 10-6 was achieved through 16 symbol per bit redundancy with 8x oversampling resulting to a maximum packet time of about 1.5ms. To relax the oscillator specifications, an 8-bit tunable oscillator was utilized with corresponding frequency and phase locking techniques. The demodulation blocks were implemented using standard threshold volatage standard cells at 3.6MHz in 500mV supply with about 100ns (1.5x operating frequency) margin to compensate for PVT variations. Given these constraints, the whole system consumes 1mW during receive states while operating below the overall average power budget of 1µW. The digital demodulator presents an area and power overhead of 33.5% and 30.5%, respectively, to the node controller, and a very negligible overhead (both < 0.1%) relative to the whole sensor node.