00000cmm a22000004i 4500 UP-99796217611211893 Buklod 20140423123443.0 m go j cr cn |||aaaaa 110816s2011 xx u | eng d 9783642195686 (eBook) 3642195687 (eBook) (iLib)UPD-00214608022 DML eng DMLUC TK 7874.66 L69 2011eb Low power and reliable SRAM memory cell and array design [electronic resource] Koichiro Ishibashi, Kenichi Osada. Berlin Heidelberg Springer 2011. 1 online resource (xi, 143 p.) Preface -- Introduction -- Fundamentals of SRAM Memory Cell -- Electrical Stability -- Sensitivity Analysis -- Memory Cell Design Technique for Low Power SOC -- Array Design Techniques -- Dummy Cell Design -- Reliable Memory Cell Design -- Future Technologies. IP-based subscription, access limited to within on-campus network. Access via Electronic Resources of the UPD University Library Website. Success in the development of recent advanced semiconductor device technologies is due to the success of SRAM memory cells. This book addresses various issues for designing SRAM memory cells for advanced CMOS technology. To study LSI design, SRAM cell design is the best materials subject because issues about variability, leakage and reliability have to be taken into account for the design. Electronic reproduction. New York SpringerLink 2011. Available via World Wide Web through SprinerLink. Electronic books. Low voltage integrated circuits Design and construction. Integrated circuits Large scale integration Design and construction. Semiconductor storage devices. Ishibashi, Koichiro. Osada,Kenichi. SpringerLink (Online service). Available for University of the Philippines Diliman via SpringerLink.Click here to access http://link.springer.com/book/10.1007/978-3-642-19568-6 FO Monograph UPD DMLR Electronic Resource