High-Level Verification Methods and Tools for Verification of System-Level Designs

High-Level Verification Methods and Tools for Verification of System-Level Designs

This book looks at the problem of design verification with a view towards speeding up the process of verification by developing methods that apply to levels of abstraction above RTL or synchronous logic descriptions. Typically such descriptions capture design functionality at the system level, hence...

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Pubblicato in:Springer eBooks.
Autori principali: Kundu, Sudipta (Autore), Lerner, Sorin (Autore), Gupta, Rajesh K. (Autore)
Ente Autore: SpringerLink (Online service)
Natura: Electronic Resource
Lingua:English
Pubblicazione: New York, NY Springer New York 2011.
Soggetti:
Integrated circuits > Verification.
Systems on a chip > Testing.
Systems on a chip > Design.
Electronic book.
Accesso online:Available for University of the Philippine Diliman via Springerlink. Click here to access