00000ctm a22000004a 4500 UP-99796217611190157 Buklod 20230215105418.0 m |o d | ta 140411s xx d r |||| u| (iLib)UPD-00214606889 DENGII eng DMLUC LG 993.5 2011 E64 B37 Barahan, Nicole John Antonio SCARM a memory simulator with a compiler-assembler for the 32-bit ARM7 microprocessor Nicole John Antonio Barahan, John Jerico Manuel Custodio. 2011. x, 69 leaves ill. + 1 CD-ROM (4 3/4 in.), 1 user manual Undergraduate student project (B.S. Computer Engineering)--University of the Philippines, Diliman. The advent of multicore technology in the domain of embedded systems is inevitable. Aside from the need to redesign programs and compilers to fully exploit the multicore architectures through uniform load distribution, the limited memory of target systems and pushes developers to focus as well on optimizing memory allocation for maximized data storage. Furthermore, designer-friendly development interfaces have become crucial in readily viewing system statistics, and testing and gauging functionality and performance. This project is an implementation of a runtime memory simulator with a compiler-assembler for the ARM7 microprocessor with multi-core and floating point operation capability. Compiler support is extended to floating point computations. Also, the integrated development environment (IDE) features selective optimization for compilation. The target outputs are the assembly codes following the instruction set architecture (ISA) of the ARM7 and the equivalent binary instructions to generate the testbench for Synopsys VCS verification. The machine dependent optimizations of the compiler concentrate on register allocation and instruction scheduling techniques to further take advantage of the ARM7 architecture. Microprocessors Design and construction. RISC microprocessors. ARM7 microprocessors. Custodio, John Jerico Manuel. Thesis FI UP UPD DENG-II LG 993.5 2011 E64 B37 Thesis