Power reduction techniques and BIST implementation on a DLX microprocessor using a 90nm CMOS process - Agbayani, Jay-ar Anacleto (2010)
As integrated circuits become more complex, the need for efficient chip testing arises. The addition of external automated test equipment (ATE) is a common solution to this need. However, ATE increases the cost of testing in terms of time and resources. An alternative to this is the implementation of a Built-In Self Test circuitry on the chip design. Previous studies have shown that the incorporation of BIST to microprocessors results to an increased power comsumption and die area, and a reduced performance. Succeeding implementations tried to deal with the increased power consumption by applying certain power reduction techniques. However, they dealt with power reduction in the test mode of the microprocessor only. The objective of the project is to implement a BIST architecture for the DLX microprocessor and to reduce its power consumption in both normal and test modes. This involves applying the STUMPS Partial Scan technique and implementing power reduction techniques that include clock gating, pattern suppression, and toggle suppression. The implemented microprocessor (power reduced DLX with partial scan BIST) is compared to the base DLX and DLX with partial scan BIST cores in terms of speed, area and power consumption. The addition of the STUMPS partial scan BIST decreased the maximum operating frequency by 31.78%, increased the area by 3.66% and power consumption by 6.96% with respect to the base core. Comparing the DLX with partial scan and the power reduced DLX with partial scan, an increase of 29% was observed for the maximum operating frequency, 15.88% area overhead, and 26.31% power reduction for the normal mode operation and 30.82% for the test mode operation.