Implementation of local voltage dithering on the ARM7 microprocessor in a 90nm CMOS process - Cada, Mark Angelo A. (2011)
Power consumption has been a critical design concern over recent years due to the energy required by portable or mobile devices versus available energy supplied by batteries. Power density also continues to increase as device densities and clock frequencies have increased dramatically in CMOS devices. The three main sources of power consumption are dynamic switching, short circuit and leakage power, of which the dynamic switching power accounts for about 90 percent of the total dissipated power. Different techniques are used to lower the power consumption in today's chips. One of which is to use local voltage dithering (LVD) that involves using multiple supply voltages and header switches to connect blocks to different stable supply voltages, depending on the timing specifications of the blocks. This document presents the implementation of local voltage dithering (LVD) to specific datapath elements, i.e. ALU, barrel shifter, and multiplier, using the original RTL codes of the blocks from the base core and coded Unified Power Format (UPF) files, which describes the power requirements of the design. The blocks were divided into indiviual power domains and dithered depending on the instruction being executed. Level restorers were used to ensure that outputs of the different power domains are of the same voltage levels. A voltage scheduler block (VSB) was added to control the switching of voltages. This project was coded using Verilog HDL, simulated using Synopsys VCS and MVSIM, and synthesized using 90nm standard cells and Synopsys Design Compiler. The total average power consumption of the microprocessor increased from 2.5 mW to 2.75 mW after adding header switches and level shifters, but decreased to 2.70 mW after applying LVD to the datapath blocks. The additional VSB contributed about 0.13% to the total average power. The datapath was able to function properly at a maximum operating frequency of 100 MHz.