A method for timing closure in supply voltage scaled CMOS digital circuits with dual-Vth devices - Luna, Anne Lorraine S. (Quezon City College of Engineering, University of the Philippines Diliman, 2013)
Power has become a dominant problem of chip designers nowadays. Thus, scaling down the supply voltage beyond the nominal has been a popular solution to significantly decrease the power consumptions of circuits. However, the lack of standard cell library characterizations at lower supply voltages prevents teh synthesis of low voltage designs using the traditional semi-custom design flow. An alternative solution is to characterize the process technology through representative circuits and estimate the timing characteristics of synthesized designs at lower supply voltages. However, this approach does not always guarantee the timing at lower voltages especially when multi-Vth devices are used in the circuit. At the nominal voltage, devices with distinct Vth have different delays and at lower voltages, their delays also degrade at different rates. This behavior can make a non-critical path with slow high Vth devices at the nominal voltage at risk of becoming the critical path at lower voltages. This new and slower critical path at low voltage requires a longer clock period than expected, leading to timing errors. This work presents a general theoretical framework for approximating and correcting the timing characteristics of circutis with multi-Vth devices taking into account their behavior at lower voltages. The proposed framework is able to model critical and non-critical paths in a dual-Vth circuit and is able to show the potential violating non-critical paths by setting a maximum delay criterion at nominal voltage. Following this maximum delay criterion, timing errors can be prevented and the dual-Vth circuit can achieve an increase in speed at the cost of minimal power overhead depending on circuit topology. To test the framework, process parameters are extracted in the 65nm CMOS technology and a synthesis flow that makes use of the extracted parameters in performing the approximation and correction is created. An 8-bit microcontroller core design is used as an input to the flow to validate the framework in a deep sub-micron digital circuit. For this dual-Vth circuit design, constraining the delay of the violating paths resulted in a 2.4x increase in speed at the 3.0V target voltage when compared to the unconstrained design. Circuit level testing, however showed that the modifications incurred a 2x increase in power and 1.25x increase energy.
Thesis (M.S. Electrical Engineering)--University of the Philippines, Diliman.
Keywords: Low voltage integrated circuits -- Design and construction; Low voltage systems