Cita APA (7th ed.)

Luna, A. L. S. (2013). A method for timing closure in supply voltage scaled CMOS digital circuits with dual-Vth devices. College of Engineering, University of the Philippines Diliman.

Cita Chicago (17th ed.)

Luna, Anne Lorraine S. A Method for Timing Closure in Supply Voltage Scaled CMOS Digital Circuits with Dual-Vth Devices. Quezon City: College of Engineering, University of the Philippines Diliman, 2013.

Cita MLA (9th ed.)

Luna, Anne Lorraine S. A Method for Timing Closure in Supply Voltage Scaled CMOS Digital Circuits with Dual-Vth Devices. College of Engineering, University of the Philippines Diliman, 2013.